High-performance computer (“HPC”) systems typically include many processors, each with its own local memory. At least some pairs of the processors are interconnected via links to enable each processor to access memory (“non-local memory”) of each, or at least some, of the other processors. Some such systems are constructed according to non-uniform memory access (“NUMA”) designs, in which access to non-local memory is slower than access to local memory. Because a HPC system may not include a separate link between every pair of processors, some non-local memory accesses are routed through third (or more) processors, thereby traversing multi-hop routes. However, determining routes quickly for each non-local memory access poses problems. Furthermore, congested links or routes retard non-local memory accesses, thereby negatively impacting performance of the affected processor(s).